Megadrive/Genesis expansion bus control signals

By David Senabre, 2006
Revisited: 2007.

There're many control signals in Megadrive, and some of them are only avaiable in the expansion bus.

/CAS_0 is a reads 000000-7FFFFF strobe. It acts as a /OE signal.
/ASEL is a read and write 000000-7FFFFF strobe. Pulse width is 220ns.
/CAS_2 is a read and write 000000-7FFFFF strobe. Pulse width is 150ns.
/ROM is a $000000-$1FFFFF strobe. This is used as /CE by any code running from expansion port. Pulse width is 330ns.

Initially, I thought /ROM was a $000000-$03FFFF strobe, to enable the 256K addresses that can be accessed in the expansion bus. But it isn't.
When a cartridge is inserted (/CART_IN low), and code is run from there, /ROM becomes a $400000-$5FFFFF strobe.

There're other signals , /FDWR, /FDC and /DISK, that seem to be used a A12000-A120FF strobe when cart is inserted (/CART_IN low).

/FDWR is a write A12000-A120FF strobe
/DISK and /FDC is a reads and write A12000-A120FF strobe

/DISK and /FDC do basically the same. I find no reason for this. I suppose one of them is used by Sega CD registers mapped to $A120xx.
But, when running code form expansion port (/CART_IN high) /FDWR asserts everytime you access $000000-$3FFFFF. It does not for RAM accesses (neither reads or writes). Pulse's width is same as CAS_2.

Some signals are not avaiable in the expansion port, and are accessible only at cartridge port.

/CE_0 is a read and write 000000-3FFFFF strobe. This one is used as /CE by game cartridges.
/TIME is a read and write A13000-A130FF strobe

According to what I read, /CAS_2 is the longest pulse when a cartridge is inserted (/CART_IN low). It is not the case when running code from expansion port.

You can see details in the timing diagram.

/OE is CAS_0.
The first /LWR pulse is a low byte write to $040001.
The next /LWR pulse is a low byte write to $200001.
You can see here, that /ROM asserts for addresses above $03FFFF and below $200000.
Thus, it confirms the supposition of it being a $000000-$1FFFFF strobe.

Again,
/ROM pulses are 330ns wide.
/ASEL pulses are 220ns wide.
/CAS2 pulses are 150ns wide.
You can see larger pulses at the begining. (600, 500 and 420 ns respectivily). This seems to occurs when accesing an address out of ROM or RAM, and affects /CAS_0, /CE_0, /DTACK too. All these signals are widened about 2 more CPU clocks (about 270-280ns). Then, the rest are of pulses of the above mentiones wides.

As /CAS_0 (/OE) asserts for 330ns, memory acces time must be 330 ns or lower for it to work on Genesis. This is quite low speed, and any memory chip will match this specification. SNES demands 200ns or even 120ns access time ROMs, depengin on if it's working in slow or high speed ROM mode.

/LWR and /UWR strobes assert for 200ns, but theoricaly, these signals only affect write operations, and determine the maximun write time a memory can have for it to work on this system. But should not constrain ROM speed. This doesn't really matter, as no memory chip is slower than 200ns nowadays.